Attachment 12006 Details for Bug 44472 – 22.2.1..22.2.2

[patch] 22.2.1..22.2.2

22.2.1-2.diff (text/plain), 161.36 KB, created by Valery Inozemtsev on 2022-12-01 12:21:10 MSK

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Creator: Valery Inozemtsev

Created: 2022-12-01 12:21:10 MSK

Size: 161.36 KB

patch

obsolete

>diff --git a/.pick_status.json b/.pick_status.json
>index b5decb00f5c..d8997106407 100644
>--- a/.pick_status.json
>+++ b/.pick_status.json
>@@ -1,4 +1,3388 @@
> [
>+    {
>+        "sha": "b02e9ef35a0446019cda9473e4c355c7cc4bb24d",
>+        "description": "anv: fill AlphaToCoverageEnable lazily from state",
>+        "nominated": false,
>+        "nomination_type": null,
>+        "resolution": 4,
>+        "main_sha": null,
>+        "because_sha": null
>+    },
>+    {
>+        "sha": "9f7535564345396de07ce59dcced593e885e15ec",
>+        "description": "anv: move emit_shading_rate to gfx8_cmd_buffer",
>+        "nominated": false,
>+        "nomination_type": null,
>+        "resolution": 4,
>+        "main_sha": null,
>+        "because_sha": null
>+    },
>+    {
>+        "sha": "83ebd637d516d5fbb2d4d998bd5a124993a4f6a8",
>+        "description": "d3d10ump: No need define snprintf anymore in InputAssembly.cpp",
>+        "nominated": false,
>+        "nomination_type": null,
>+        "resolution": 4,
>+        "main_sha": null,
>+        "because_sha": null
>+    },
>+    {
>+        "sha": "a9da108c6b511cb74bfd89a4ce7658ffae288fd7",
>+        "description": "nir: No need redefine snprintf anymore in nir.h",
>+        "nominated": false,
>+        "nomination_type": null,
>+        "resolution": 4,
>+        "main_sha": null,
>+        "because_sha": null
>+    },
>+    {
>+        "sha": "1ee21139e84815f75389bb9b633bfecc1917d533",
>+        "description": "gallium: delete graw",
>+        "nominated": false,
>+        "nomination_type": null,
>+        "resolution": 4,
>+        "main_sha": null,
>+        "because_sha": null
>+    },
>+    {
>+        "sha": "ac7f4e0942de2576feda085d5fd165323753f950",
>+        "description": "glsl/glsl_to_nir: remove unreachable code",
>+        "nominated": false,
>+        "nomination_type": null,
>+        "resolution": 4,
>+        "main_sha": null,
>+        "because_sha": null
>+    },
>+    {
>+        "sha": "c7e92686583f45617aa017f30f93d156f2a74a2c",
>+        "description": "radv: fix setting results for initialization failures in thread trace and trap handler",
>+        "nominated": false,
>+        "nomination_type": null,
>+        "resolution": 4,
>+        "main_sha": null,
>+        "because_sha": null
>+    },
>+    {
>+        "sha": "0e782d96095aecfbc43233b9358e8bf915b26062",
>+        "description": "radeonsi: Inherit the old modifier when reallocating the texture.",
>+        "nominated": false,
>+        "nomination_type": null,
>+        "resolution": 4,
>+        "main_sha": null,
>+        "because_sha": null
>+    },
>+    {
>+        "sha": "5bc52a9103d2de45353056734ca1a9e94e9f6e94",
>+        "description": "anv: fix FTBFS on grl due to changes in clang 15",
>+        "nominated": false,
>+        "nomination_type": null,
>+        "resolution": 4,
>+        "main_sha": null,
>+        "because_sha": null
>+    },
>+    {
>+        "sha": "2c7be4d4212a7b6c50523285b412d5747231323e",
>+        "description": "nir: Usher nir_normalize_cubemap_coords into 2022",
>+        "nominated": false,
>+        "nomination_type": null,
>+        "resolution": 4,
>+        "main_sha": null,
>+        "because_sha": null
>+    },
>+    {
>+        "sha": "fc5c671e8785c89cf986181e0e3e7fa8742c4dce",
>+        "description": "nir: Fix nir_fmax_abs_vec_comp",
>+        "nominated": true,
>+        "nomination_type": 1,
>+        "resolution": 1,
>+        "main_sha": null,
>+        "because_sha": "272e927d0e9fed6e791d706ff5d895b6c2036fc0"
>+    },
>+    {
>+        "sha": "6fbb87851cda10cde7bf42fb8d391420cf3657b1",
>+        "description": "d3d12: HEVC Set D3D12_VIDEO_ENCODER_CODEC_CONFIGURATION_HEVC_FLAG_USE_ASYMETRIC_MOTION_PARTITION when required by caps",
>+        "nominated": false,
>+        "nomination_type": null,
>+        "resolution": 4,
>+        "main_sha": null,
>+        "because_sha": null
>+    },
>+    {
>+        "sha": "8f654b90005b75a74796d36d980676ce1d739d12",
>+        "description": "d3d12: Fix HEVC wrong caps detection due to bad parenthesis in condition",
>+        "nominated": false,
>+        "nomination_type": null,
>+        "resolution": 4,
>+        "main_sha": null,
>+        "because_sha": null
>+    },
>+    {
>+        "sha": "be7e2e5525b89fbd532b5fa7ef36bbd72b72956e",
>+        "description": "d3d12: HEVC Encode workaround for edge case in caps reporting not contemplated by upper layer interface",
>+        "nominated": false,
>+        "nomination_type": null,
>+        "resolution": 4,
>+        "main_sha": null,
>+        "because_sha": null
>+    },
>+    {
>+        "sha": "3eed5931edf6e5f45378b013ca21f98f17af2b34",
>+        "description": "tu: Fix the size of patch control points state",
>+        "nominated": false,
>+        "nomination_type": 1,
>+        "resolution": 4,
>+        "main_sha": null,
>+        "because_sha": "68f3c38c8011e3ff304a67b6ffb33fd21ee65b0c"
>+    },
>+    {
>+        "sha": "ebf7f7a1827006394fc6355ee245e45b6cfe2793",
>+        "description": "aco/spill: Fix spilling of Phi operands",
>+        "nominated": true,
>+        "nomination_type": 0,
>+        "resolution": 1,
>+        "main_sha": null,
>+        "because_sha": null
>+    },
>+    {
>+        "sha": "829f769e602a7bbff4a0603076cb74ce9a966e8e",
>+        "description": "pan/mdg: Fix 16-bit alignment with spiller",
>+        "nominated": true,
>+        "nomination_type": 1,
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>+        "main_sha": null,
>+        "because_sha": "129d390bd8cc50f55b748ae6e95bed8c6074a488"
>+    },
>+    {
>+        "sha": "2c446b66364bff90012262c6960a8d28d3593e3d",
>+        "description": "pan/mdg: Limit work registers for large workgroups",
>+        "nominated": true,
>+        "nomination_type": 0,
>+        "resolution": 0,
>+        "main_sha": null,
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>+    },
>+    {
>+        "sha": "9b19104a30bba35c4025833d5022c8ddc6c1ccd0",
>+        "description": "pan/mdg: Lower PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK on Midgard",
>+        "nominated": true,
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>+        "resolution": 1,
>+        "main_sha": null,
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>+        "description": "panfrost/ci: Remove stale fail",
>+        "nominated": false,
>+        "nomination_type": null,
>+        "resolution": 4,
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>+        "because_sha": null
>+    },
>+    {
>+        "sha": "16d061d3acd475c1f59e3c71c160a78933169c05",
>+        "description": "anv: Enable 16 bit float ops on devices that have a LSC",
>+        "nominated": false,
>+        "nomination_type": null,
>+        "resolution": 4,
>+        "main_sha": null,
>+        "because_sha": null
>+    },
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>+        "nominated": false,
>+        "nomination_type": null,
>+        "resolution": 4,
>+        "main_sha": null,
>+        "because_sha": null
>+    },
>+    {
>+        "sha": "2e774180c61b7928329fb38652d2a54d0495c9e2",
>+        "description": "Revert \"panfrost/ci: Disable t720 jobs\"",
>+        "nominated": false,
>+        "nomination_type": 2,
>+        "resolution": 4,
>+        "main_sha": null,
>+        "because_sha": "b3a69d1c31a0c4073e7865945b9f70f96be6c34e"
>+    },
>+    {
>+        "sha": "c1cb7506bb39843384b5b6114cd8690a38655ef3",
>+        "description": "v3dv/pipeline: keep qpu_insts around if we expect them to be used later",
>+        "nominated": false,
>+        "nomination_type": null,
>+        "resolution": 4,
>+        "main_sha": null,
>+        "because_sha": null
>+    },
>+    {
>+        "sha": "7dcdd519385aaa4fddfa1368fbbbc89c408befe3",
>+        "description": "glthread: leave dlist dispatch in place for Begin/End",
>+        "nominated": true,
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>+        "resolution": 1,
>+        "main_sha": null,
>+        "because_sha": "7f1cac7ba682410214289084dcc272167ca44e6b"
>+    },
>+    {
>+        "sha": "ca02da294ad02ff3bce8a0a37bc5d84823879e42",
>+        "description": "radv: discard the PS epilog when the pipeline doesn't use a fragment shader",
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>+        "resolution": 4,
>+        "main_sha": null,
>+        "because_sha": null
>+    },
>+    {
>+        "sha": "7b3aae89126dcdce4ec364fe0329a533c736d105",
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>+        "nominated": false,
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>+        "resolution": 4,
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>+    },
>+    {
>+        "sha": "c8849043a843140396f4874fed95f6c08ad587ee",
>+        "description": "Revert \"CI: Igalia farm is down\"",
>+        "nominated": false,
>+        "nomination_type": 2,
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>+        "because_sha": "aa405b789ebf1797fdb3a1891fac49d0cca21c42"
>+    },
>+    {
>+        "sha": "675bcbb7a1c0111dc907f189b4a2de18397e6f23",
>+        "description": "mesa: add EXT_debug_label support",
>+        "nominated": false,
>+        "nomination_type": null,
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>+    },
>+    {
>+        "sha": "70fef476334297c51ed237aa3044e3003ffd5a5e",
>+        "description": "ci/windows: Getting the default supported windows version to be 7 when using mingw",
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>+    },
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>+        "sha": "79891bea1cbca4b822a8ccfd7cd4c05099ff68c5",
>+        "description": "ci/windows: Remove -Dlibelf:warning_level=1 as libelf subproject are already removed",
>+        "nominated": false,
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>+    {
>+        "sha": "2cb21fdd53fd50b6d3f15e114beb981b347a6e14",
>+        "description": "ci/windows: Enable gles1 for msvc",
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>+        "because_sha": null
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>+        "sha": "6905c258298b8cf6653692a82dd1473936b8a766",
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>+        "sha": "43756a9f76e46bed894e679b7ca9286315e428fe",
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>+        "sha": "e8547392b029959e4f76b1e4ad9d4fe71255bd72",
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>+        "sha": "d83176d1c073f7f4d33393a235113d43915faff9",
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>+        "description": "mesa/main: remove driver-cap for ARB_point_sprite",
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>+        "sha": "b0d698c5328fbcb5e0ae3952cde1c1e411151adb",
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>+        "sha": "17d8ff3a398027d23b7caa6c174ca654c9875284",
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>+        "sha": "510a34fbf33918a67f6a2e7277480cb02e1ca172",
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>+        "sha": "8616f11a395e8578e6e58500e30e426e92d7337c",
>+        "description": "anv: track descriptor set layout flags",
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>+        "sha": "d7f1569307b44a2b151f5461e69fb342b7fc7d15",
>+        "description": "anv: limit push constant reemission",
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>+    {
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>+        "resolution": 1,
>         "main_sha": null,
>         "because_sha": "5b683ba19ac77d6c7dfd8de478678d0b90ba764f"
>     },
>@@ -19174,7 +22558,7 @@
>         "description": "d3d12: Implement cap PIPE_VIDEO_SUPPORTS_CONTIGUOUS_PLANES_MAP",
>         "nominated": true,
>         "nomination_type": 1,
>-        "resolution": 0,
>+        "resolution": 1,
>         "main_sha": null,
>         "because_sha": "a585d95803ca38d42b893603a85bf6442a54838a"
>     },
>@@ -19183,7 +22567,7 @@
>         "description": "gallium/va: vaDeriveImage to check PIPE_VIDEO_SUPPORTS_CONTIGUOUS_PLANES_MAP",
>         "nominated": true,
>         "nomination_type": 1,
>-        "resolution": 0,
>+        "resolution": 1,
>         "main_sha": null,
>         "because_sha": "a585d95803ca38d42b893603a85bf6442a54838a"
>     },
>@@ -21991,7 +25375,7 @@
>         "description": "nir: spirv: Allow 32-bit version of nir_intrinsic_is_sparse_texels_resident",
>         "nominated": true,
>         "nomination_type": 1,
>-        "resolution": 0,
>+        "resolution": 3,
>         "main_sha": null,
>         "because_sha": "4cbdf9ec4d454c4df157570387edeeaf45847b8a"
>     },
>diff --git a/VERSION b/VERSION
>index ab3d3062f4c..bd2f90fb0e8 100644
>--- a/VERSION
>+++ b/VERSION
>@@ -1 +1 @@
>-22.2.1
>\ No newline at end of file
>+22.2.2
>\ No newline at end of file
>diff --git a/docs/relnotes/22.2.1.rst b/docs/relnotes/22.2.1.rst
>index aea4cae3f6a..97afc7e9a05 100644
>--- a/docs/relnotes/22.2.1.rst
>+++ b/docs/relnotes/22.2.1.rst
>@@ -19,7 +19,8 @@ SHA256 checksum
> 
> ::
> 
>-    TBD.
>+    0079beac0a33f45e7e0aec59e6913eafbc4268a3f1e2e330017440494f91b13c  mesa-22.2.1.tar.xz
>+
> 
> 
> New features
>diff --git a/docs/relnotes/22.2.2.rst b/docs/relnotes/22.2.2.rst
>new file mode 100644
>index 00000000000..e3e32756a83
>--- /dev/null
>+++ b/docs/relnotes/22.2.2.rst
>@@ -0,0 +1,144 @@
>+Mesa 22.2.2 Release Notes / 2022-10-19
>+======================================
>+
>+Mesa 22.2.2 is a bug fix release which fixes bugs found since the 22.2.1 release.
>+
>+Mesa 22.2.2 implements the OpenGL 4.6 API, but the version reported by
>+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
>+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
>+Some drivers don't support all the features required in OpenGL 4.6. OpenGL
>+4.6 is **only** available if requested at context creation.
>+Compatibility contexts may report a lower version depending on each driver.
>+
>+Mesa 22.2.2 implements the Vulkan 1.3 API, but the version reported by
>+the apiVersion property of the VkPhysicalDeviceProperties struct
>+depends on the particular driver being used.
>+
>+SHA256 checksum
>+---------------
>+
>+::
>+
>+    TBD.
>+
>+
>+New features
>+------------
>+
>+- None
>+
>+
>+Bug fixes
>+---------
>+
>+- radv: Crash in dEQP-VK.ray_query.misc.dynamic_indexing
>+- glthread: radeonsi: offset textures in game starsector with glthread enabled
>+- Crashing on Windows VM
>+- Exanima renders with the wrong colors.
>+- nouveau: tegra124: GL_OUT_OF_MEMORY error
>+
>+
>+Changes
>+-------
>+
>+Alejandro Tafalla (1):
>+
>+- freedreno: Fix graphic glitches on a4xx and a5xx
>+
>+Alyssa Rosenzweig (4):
>+
>+- nir/lower_system_values: Fix cs_local_index_to_id with variable workgroups
>+- pan/mdg: Lower PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK on Midgard
>+- pan/mdg: Fix 16-bit alignment with spiller
>+- nir: Fix nir_fmax_abs_vec_comp
>+
>+Andri Yngvason (1):
>+
>+- gallium/vl: Add opaque rgb pixel formats
>+
>+Daniel SchÃ¼rmann (1):
>+
>+- aco/spill: Fix spilling of Phi operands
>+
>+Danylo Piliaiev (1):
>+
>+- tu: Reset whether there is DS resolve for dynamic subpass
>+
>+Dave Airlie (1):
>+
>+- gallivm: handle llvm coroutines for llvm > 15
>+
>+Diogo Ivo (1):
>+
>+- nouveau: treat DRM_FORMAT_INVALID as implicit modifier
>+
>+Dylan Baker (7):
>+
>+- docs: Add sha256 sum for 22.2.1
>+- .pick_status.json: Update to 243aa6b2ec0c2626b1333ba666a6d6d60ede8505
>+- .pick_status.json: Update to c4482a3c1a973975eb27ac284a18bebca24f7876
>+- .pick_status.json: Update to 3eed5931edf6e5f45378b013ca21f98f17af2b34
>+- .pick_status.json: Update to b02e9ef35a0446019cda9473e4c355c7cc4bb24d
>+- .pick_status.json: Mark 4c7a44413a07d3fb314f786e047bb7212c082a6c as denominated
>+- .pick_status.json: Mark dbd022f2ab43ff0a9ecc05c61123467e25f109de as backported
>+
>+Emma Anholt (1):
>+
>+- turnip: Don't use the dynamic color write enable during non-dynamic.
>+
>+Erik Faye-Lund (1):
>+
>+- gallium/u_threaded_context: remove stale comment
>+
>+Filip Gawin (1):
>+
>+- r300: don't use smooth line if not requested
>+
>+Gert Wollny (3):
>+
>+- r600/sfn: Always start a new CF after a KILL instruction
>+- r600/sfn: don't propagate registers into conditional test
>+- virgl: Report CONSTANT_BUFFER_SIZE according to GL_MAX_UNIFORM_BLOCK_SIZE
>+
>+Lionel Landwerlin (3):
>+
>+- vulkan/runtime: don't lookup the pipeline disk cache if disabled
>+- anv: initialization pipeline layout to 0s
>+- anv: add missing tracepoint
>+
>+Liviu Prodea (1):
>+
>+- clc/clover: Link clang statically when shared-llvm is disabled
>+
>+Mike Blumenkrantz (3):
>+
>+- zink: clamp line_stipple_factor to 1 if stipple is disabled
>+- zink: unset rp_changed after initializing renderpass attachments
>+- zink: disable fbfetch when flushing clears
>+
>+Ryan Houdek (1):
>+
>+- vulkan/wsi: Add dep_libudev to idep dependencies
>+
>+Sil Vilerino (2):
>+
>+- gallium/va: vaDeriveImage to check PIPE_VIDEO_SUPPORTS_CONTIGUOUS_PLANES_MAP
>+- d3d12: Implement cap PIPE_VIDEO_SUPPORTS_CONTIGUOUS_PLANES_MAP
>+
>+SoroushIMG (3):
>+
>+- zink: fix invalid Offset set for variables which do not need an offset
>+- zink: stop enabling minmax filtering when not supported
>+- zink: fix isNan mismatch between NIR and SPIR-V
>+
>+Timothy Arceri (5):
>+
>+- util/conf: enable init to zero workaround for Exanima
>+- util/radeonsi: enable zerovram workaround for Exanima
>+- radv: add radv_zero_vram workarounds for OpenGL games
>+- glthread: fix matrix stack depth tracking
>+- glthread: leave dlist dispatch in place for Begin/End
>+
>+Yonggang Luo (1):
>+
>+- util: Turn -DWINDOWS_NO_FUTEX to be pre_args
>diff --git a/meson.build b/meson.build
>index cae1e4b5834..1550bb208a9 100644
>--- a/meson.build
>+++ b/meson.build
>@@ -1630,7 +1630,7 @@ endif
> dep_futex = null_dep
> if host_machine.system() == 'windows'
>   if (get_option('min-windows-version') < 8)
>-    dep_futex = declare_dependency(compile_args : ['-DWINDOWS_NO_FUTEX'])
>+    pre_args += '-DWINDOWS_NO_FUTEX'
>   else
>     dep_futex = cc.find_library('synchronization', required : true)
>   endif
>@@ -1876,7 +1876,7 @@ if with_clc
> 
>   dep_clang = cpp.find_library('clang-cpp', dirs : llvm_libdir, required : false)
> 
>-  if not dep_clang.found()
>+  if not dep_clang.found() or not _shared_llvm
>     clang_modules = [
>       'clangBasic', 'clangAST', 'clangCodeGen', 'clangLex',
>       'clangDriver', 'clangFrontend', 'clangFrontendTool',
>diff --git a/src/amd/compiler/aco_spill.cpp b/src/amd/compiler/aco_spill.cpp
>index e712920f53e..38a5cf8d475 100644
>--- a/src/amd/compiler/aco_spill.cpp
>+++ b/src/amd/compiler/aco_spill.cpp
>@@ -920,8 +920,10 @@ add_coupling_code(spill_ctx& ctx, Block* block, unsigned block_idx)
>                   pred.instructions[idx]->opcode != aco_opcode::p_logical_end);
>          std::vector<aco_ptr<Instruction>>::iterator it = std::next(pred.instructions.begin(), idx);
>          pred.instructions.insert(it, std::move(spill));
>+
>+         /* Add the original name to predecessor's spilled variables */
>          if (spill_op.isTemp())
>-            ctx.spills_exit[pred_idx][spill_op.getTemp()] = spill_id;
>+            ctx.spills_exit[pred_idx][phi->operands[i].getTemp()] = spill_id;
>       }
> 
>       /* remove phi from instructions */
>diff --git a/src/amd/vulkan/00-radv-defaults.conf b/src/amd/vulkan/00-radv-defaults.conf
>index c095d06f814..948330ebe6d 100644
>--- a/src/amd/vulkan/00-radv-defaults.conf
>+++ b/src/amd/vulkan/00-radv-defaults.conf
>@@ -166,5 +166,38 @@ Application bugs worked around in this file:
>         <application name="Melty Blood Actress Again Current Code" application_name_match="MBAA.exe">
>             <option name="radv_disable_dcc" value="true" />
>         </application>
>+
>+        
>+        <application name="Black Geyser: Couriers of Darkness" executable="BlackGeyser.x86_64">
>+            <option name="radv_zero_vram" value="true" />
>+        </application>
>+
>+        
>+        <application name="7 Days to Die" executable="7DaysToDie.x86_64">
>+            <option name="radv_zero_vram" value="true" />
>+        </application>
>+        <application name="7 Days to Die" executable="7DaysToDie.x86">
>+            <option name="radv_zero_vram" value="true" />
>+        </application>
>+
>+        <application name="Monolith demo5" executable="runner" sha1="0c40d509a74e357f0280cb1bd882e9cd94b91bdf">
>+            <option name="radv_zero_vram" value="true" />
>+        </application>
>+
>+        <application name="American Truck Simulator" executable="amtrucks">
>+            <option name="radv_zero_vram" value="true" />
>+        </application>
>+
>+        <application name="Counter-Strike Global Offensive" executable="csgo_linux64">
>+            <option name="radv_zero_vram" value="true" />
>+        </application>
>+
>+        <application name="Exanima" executable="Exanima.exe">
>+            <option name="radv_zero_vram" value="true"/>
>+        </application>
>+
>+        <application name="Rocket League" executable="RocketLeague">
>+            <option name="radv_zero_vram" value="true" />
>+        </application>
>     </device>
> </driconf>
>diff --git a/src/compiler/nir/nir_builtin_builder.h b/src/compiler/nir/nir_builtin_builder.h
>index 40983a26456..97a4e4d3010 100644
>--- a/src/compiler/nir/nir_builtin_builder.h
>+++ b/src/compiler/nir/nir_builtin_builder.h
>@@ -62,9 +62,10 @@ nir_nan_check2(nir_builder *b, nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *res)
> static inline nir_ssa_def *
> nir_fmax_abs_vec_comp(nir_builder *b, nir_ssa_def *vec)
> {
>-   nir_ssa_def *res = nir_channel(b, vec, 0);
>+   nir_ssa_def *abs = nir_fabs(b, vec);
>+   nir_ssa_def *res = nir_channel(b, abs, 0);
>    for (unsigned i = 1; i < vec->num_components; ++i)
>-      res = nir_fmax(b, res, nir_fabs(b, nir_channel(b, vec, i)));
>+      res = nir_fmax(b, res, nir_channel(b, abs, i));
>    return res;
> }
> 
>diff --git a/src/compiler/nir/nir_lower_system_values.c b/src/compiler/nir/nir_lower_system_values.c
>index e4698965edc..89289130e9d 100644
>--- a/src/compiler/nir/nir_lower_system_values.c
>+++ b/src/compiler/nir/nir_lower_system_values.c
>@@ -463,11 +463,9 @@ lower_compute_system_value_instr(nir_builder *b,
>           *    gl_WorkGroupSize.x + gl_LocalInvocationID.x"
>           */
>          nir_ssa_def *local_id = nir_load_local_invocation_id(b);
>-
>-         nir_ssa_def *size_x =
>-            nir_imm_int(b, b->shader->info.workgroup_size[0]);
>-         nir_ssa_def *size_y =
>-            nir_imm_int(b, b->shader->info.workgroup_size[1]);
>+         nir_ssa_def *local_size = nir_load_workgroup_size(b);
>+         nir_ssa_def *size_x = nir_channel(b, local_size, 0);
>+         nir_ssa_def *size_y = nir_channel(b, local_size, 1);
> 
>          /* Because no hardware supports a local workgroup size greater than
>           * about 1K, this calculation can be done in 32-bit and can save some
>diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c
>index 32a57c4f6e5..4109ef211b6 100644
>--- a/src/freedreno/vulkan/tu_cmd_buffer.c
>+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
>@@ -4341,10 +4341,9 @@ tu6_emit_blend(struct tu_cs *cs, struct tu_cmd_buffer *cmd)
>       }
>    }
> 
>-   uint32_t blend_enable_mask =
>-      (cmd->state.logic_op_enabled && cmd->state.rop_reads_dst) ?
>-      color_write_enable : (cmd->state.pipeline_blend_enable &
>-                            cmd->state.color_write_enable);
>+   uint32_t blend_enable_mask = color_write_enable;
>+   if (!(cmd->state.logic_op_enabled && cmd->state.rop_reads_dst))
>+      blend_enable_mask &= cmd->state.pipeline_blend_enable;
> 
>    tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
>    tu_cs_emit(cs, cmd->state.sp_blend_cntl |
>diff --git a/src/freedreno/vulkan/tu_pass.c b/src/freedreno/vulkan/tu_pass.c
>index 3ed5fb1274c..7e1629bcb73 100644
>--- a/src/freedreno/vulkan/tu_pass.c
>+++ b/src/freedreno/vulkan/tu_pass.c
>@@ -984,6 +984,7 @@ tu_setup_dynamic_render_pass(struct tu_cmd_buffer *cmd_buffer,
>    pass->attachments = cmd_buffer->dynamic_rp_attachments;
> 
>    subpass->color_count = subpass->resolve_count = info->colorAttachmentCount;
>+   subpass->resolve_depth_stencil = false;
>    subpass->color_attachments = cmd_buffer->dynamic_color_attachments;
>    subpass->resolve_attachments = cmd_buffer->dynamic_resolve_attachments;
>    subpass->feedback_invalidate = false;
>@@ -1102,6 +1103,7 @@ tu_setup_dynamic_inheritance(struct tu_cmd_buffer *cmd_buffer,
> 
>    subpass->color_count = info->colorAttachmentCount;
>    subpass->resolve_count = 0;
>+   subpass->resolve_depth_stencil = false;
>    subpass->color_attachments = cmd_buffer->dynamic_color_attachments;
>    subpass->resolve_attachments = NULL;
>    subpass->feedback_invalidate = false;
>diff --git a/src/gallium/auxiliary/draw/draw_llvm.c b/src/gallium/auxiliary/draw/draw_llvm.c
>index 4ec2883c2dd..6809966b4ae 100644
>--- a/src/gallium/auxiliary/draw/draw_llvm.c
>+++ b/src/gallium/auxiliary/draw/draw_llvm.c
>@@ -3381,7 +3381,7 @@ draw_tcs_llvm_generate(struct draw_llvm *llvm,
> 
>    LLVMSetFunctionCallConv(variant_coro, LLVMCCallConv);
> 
>-   LLVMAddTargetDependentFunctionAttr(variant_coro, "coroutine.presplit", "0");
>+   lp_build_coro_add_presplit(variant_coro);
> 
>    for (i = 0; i < ARRAY_SIZE(arg_types); ++i) {
>       if (LLVMGetTypeKind(arg_types[i]) == LLVMPointerTypeKind) {
>diff --git a/src/gallium/auxiliary/gallivm/lp_bld_coro.h b/src/gallium/auxiliary/gallivm/lp_bld_coro.h
>index 1853217ed77..e3cf415230e 100644
>--- a/src/gallium/auxiliary/gallivm/lp_bld_coro.h
>+++ b/src/gallium/auxiliary/gallivm/lp_bld_coro.h
>@@ -29,6 +29,7 @@
> #include <stdbool.h>
> #include "pipe/p_compiler.h"
> #include "gallivm/lp_bld.h"
>+#include "gallivm/lp_bld_intr.h"
> 
> struct gallivm_state;
> LLVMValueRef lp_build_coro_id(struct gallivm_state *gallivm);
>@@ -73,4 +74,14 @@ void lp_build_coro_suspend_switch(struct gallivm_state *gallivm,
> 
> void lp_build_coro_add_malloc_hooks(struct gallivm_state *gallivm);
> void lp_build_coro_declare_malloc_hooks(struct gallivm_state *gallivm);
>+
>+static inline void lp_build_coro_add_presplit(LLVMValueRef coro)
>+{
>+#if LLVM_VERSION_MAJOR >= 15
>+   lp_add_function_attr(coro, -1, LP_FUNC_ATTR_PRESPLITCORO);
>+#else
>+   LLVMAddTargetDependentFunctionAttr(coro, "coroutine.presplit", "0");
>+#endif
>+}
>+
> #endif
>diff --git a/src/gallium/auxiliary/gallivm/lp_bld_intr.c b/src/gallium/auxiliary/gallivm/lp_bld_intr.c
>index 99f5c77c4f0..d0ef1bc5d04 100644
>--- a/src/gallium/auxiliary/gallivm/lp_bld_intr.c
>+++ b/src/gallium/auxiliary/gallivm/lp_bld_intr.c
>@@ -162,6 +162,7 @@ static const char *attr_to_str(enum lp_func_attr attr)
>    case LP_FUNC_ATTR_WRITEONLY: return "writeonly";
>    case LP_FUNC_ATTR_INACCESSIBLE_MEM_ONLY: return "inaccessiblememonly";
>    case LP_FUNC_ATTR_CONVERGENT: return "convergent";
>+   case LP_FUNC_ATTR_PRESPLITCORO: return "presplitcoroutine";
>    default:
>       _debug_printf("Unhandled function attribute: %x\n", attr);
>       return 0;
>diff --git a/src/gallium/auxiliary/gallivm/lp_bld_intr.h b/src/gallium/auxiliary/gallivm/lp_bld_intr.h
>index 98dfb0d0cb3..a4a8b1900d8 100644
>--- a/src/gallium/auxiliary/gallivm/lp_bld_intr.h
>+++ b/src/gallium/auxiliary/gallivm/lp_bld_intr.h
>@@ -41,6 +41,7 @@
> #include "gallivm/lp_bld.h"
> #include "gallivm/lp_bld_init.h"
> 
>+struct lp_type;
> 
> /**
>  * Max number of arguments in an intrinsic.
>@@ -57,6 +58,7 @@ enum lp_func_attr {
>    LP_FUNC_ATTR_WRITEONLY    = LLVM_VERSION_MAJOR >= 4 ? (1 << 7) : 0,
>    LP_FUNC_ATTR_INACCESSIBLE_MEM_ONLY = LLVM_VERSION_MAJOR >= 4 ? (1 << 8) : 0,
>    LP_FUNC_ATTR_CONVERGENT   = LLVM_VERSION_MAJOR >= 4 ? (1 << 9) : 0,
>+   LP_FUNC_ATTR_PRESPLITCORO = (1 << 10),
> 
>    /* Legacy intrinsic that needs attributes on function declarations
>     * and they must match the internal LLVM definition exactly, otherwise
>diff --git a/src/gallium/auxiliary/util/u_threaded_context.h b/src/gallium/auxiliary/util/u_threaded_context.h
>index ce63e74393f..143b843c9ca 100644
>--- a/src/gallium/auxiliary/util/u_threaded_context.h
>+++ b/src/gallium/auxiliary/util/u_threaded_context.h
>@@ -532,7 +532,6 @@ struct threaded_context {
>    uint32_t image_buffers[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_IMAGES];
>    uint32_t shader_buffers_writeable_mask[PIPE_SHADER_TYPES];
>    uint64_t image_buffers_writeable_mask[PIPE_SHADER_TYPES];
>-   /* Don't use PIPE_MAX_SHADER_SAMPLER_VIEWS because it's too large. */
>    uint32_t sampler_buffers[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_SAMPLER_VIEWS];
> 
>    struct tc_batch batch_slots[TC_MAX_BATCHES];
>diff --git a/src/gallium/auxiliary/vl/vl_video_buffer.c b/src/gallium/auxiliary/vl/vl_video_buffer.c
>index a8815c4ba77..579fcfd5a0a 100644
>--- a/src/gallium/auxiliary/vl/vl_video_buffer.c
>+++ b/src/gallium/auxiliary/vl/vl_video_buffer.c
>@@ -77,7 +77,9 @@ vl_video_buffer_plane_order(enum pipe_format format)
> 
>    case PIPE_FORMAT_NV12:
>    case PIPE_FORMAT_R8G8B8A8_UNORM:
>+   case PIPE_FORMAT_R8G8B8X8_UNORM:
>    case PIPE_FORMAT_B8G8R8A8_UNORM:
>+   case PIPE_FORMAT_B8G8R8X8_UNORM:
>    case PIPE_FORMAT_YUYV:
>    case PIPE_FORMAT_UYVY:
>    case PIPE_FORMAT_P010:
>diff --git a/src/gallium/drivers/d3d12/d3d12_video_screen.cpp b/src/gallium/drivers/d3d12/d3d12_video_screen.cpp
>index a5b8cd323b4..eb649823ba0 100644
>--- a/src/gallium/drivers/d3d12/d3d12_video_screen.cpp
>+++ b/src/gallium/drivers/d3d12/d3d12_video_screen.cpp
>@@ -535,6 +535,8 @@ d3d12_screen_get_video_param_decode(struct pipe_screen *pscreen,
>          return true;
>       case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
>          return true;
>+      case PIPE_VIDEO_SUPPORTS_CONTIGUOUS_PLANES_MAP:
>+         return true;
>          break;
>       default:
>          debug_printf("[d3d12_screen_get_video_param] unknown video param: %d\n", param);
>@@ -608,6 +610,7 @@ d3d12_screen_get_video_param_postproc(struct pipe_screen *pscreen,
>       case PIPE_VIDEO_CAP_PREFERED_FORMAT:
>       case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
>       case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
>+      case PIPE_VIDEO_SUPPORTS_CONTIGUOUS_PLANES_MAP:
>       case PIPE_VIDEO_CAP_VPP_MAX_INPUT_WIDTH:
>       case PIPE_VIDEO_CAP_VPP_MAX_INPUT_HEIGHT:
>       case PIPE_VIDEO_CAP_VPP_MIN_INPUT_WIDTH:
>@@ -652,6 +655,8 @@ d3d12_screen_get_video_param_postproc(struct pipe_screen *pscreen,
>                return supportCaps.InputSample.Width;
>             } else if (param == PIPE_VIDEO_CAP_MAX_HEIGHT) {
>                return supportCaps.InputSample.Height;
>+            } else if (param == PIPE_VIDEO_SUPPORTS_CONTIGUOUS_PLANES_MAP) {
>+               return true;
>             } else if (param == PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE) {
>                return true;
>             } else if (param == PIPE_VIDEO_CAP_VPP_MAX_INPUT_WIDTH) {
>@@ -755,6 +760,8 @@ d3d12_screen_get_video_param_encode(struct pipe_screen *pscreen,
>          return false;
>       case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
>          return true;
>+      case PIPE_VIDEO_SUPPORTS_CONTIGUOUS_PLANES_MAP:
>+         return true;
>       default:
>          debug_printf("[d3d12_screen_get_video_param] unknown video param: %d\n", param);
>          return 0;
>diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
>index e8e812e2fc1..394c4ba9f0a 100644
>--- a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
>+++ b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
>@@ -146,6 +146,14 @@ use_hw_binning(struct fd_batch *batch)
> {
>    const struct fd_gmem_stateobj *gmem = batch->gmem_state;
> 
>+   /* workaround: Like on a3xx, hw binning and scissor optimization
>+    * don't play nice together.
>+    *
>+    * Disable binning if scissor optimization is used.
>+    */
>+   if (gmem->minx || gmem->miny)
>+      return false;
>+
>    if ((gmem->maxpw * gmem->maxph) > 32)
>       return false;
> 
>diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
>index b2aa4bff4e4..95847056bd9 100644
>--- a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
>+++ b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
>@@ -263,6 +263,14 @@ use_hw_binning(struct fd_batch *batch)
> {
>    const struct fd_gmem_stateobj *gmem = batch->gmem_state;
> 
>+   /* workaround: Like on a3xx, hw binning and scissor optimization
>+    * don't play nice together.
>+    *
>+    * Disable binning if scissor optimization is used.
>+    */
>+   if (gmem->minx || gmem->miny)
>+      return false;
>+
>    if ((gmem->maxpw * gmem->maxph) > 32)
>       return false;
> 
>diff --git a/src/gallium/drivers/llvmpipe/lp_state_cs.c b/src/gallium/drivers/llvmpipe/lp_state_cs.c
>index 5b26bf7265f..111434a69ba 100644
>--- a/src/gallium/drivers/llvmpipe/lp_state_cs.c
>+++ b/src/gallium/drivers/llvmpipe/lp_state_cs.c
>@@ -133,7 +133,7 @@ generate_compute(struct llvmpipe_context *lp,
> 
>    coro = LLVMAddFunction(gallivm->module, func_name_coro, coro_func_type);
>    LLVMSetFunctionCallConv(coro, LLVMCCallConv);
>-   LLVMAddTargetDependentFunctionAttr(coro, "coroutine.presplit", "0");
>+   lp_build_coro_add_presplit(coro);
> 
>    variant->function = function;
> 
>diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c b/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
>index e0a9d48249f..e93d66c71b6 100644
>--- a/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
>+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
>@@ -423,9 +423,12 @@ nvc0_miptree_select_best_modifier(struct pipe_screen *pscreen,
> 
>    for (i = 0u; i < count; i++) {
>       for (p = 0; p < ARRAY_SIZE(prio_supported_mods); p++) {
>-         if (prio_supported_mods[p] == modifiers[i]) {
>-            if (top_mod_slot > p) top_mod_slot = p;
>-            break;
>+         if (prio_supported_mods[p] != DRM_FORMAT_MOD_INVALID) {
>+            if (modifiers[i] == DRM_FORMAT_MOD_INVALID ||
>+                prio_supported_mods[p] == modifiers[i]) {
>+               if (top_mod_slot > p) top_mod_slot = p;
>+               break;
>+            }
>          }
>       }
>    }
>diff --git a/src/gallium/drivers/panfrost/pan_screen.c b/src/gallium/drivers/panfrost/pan_screen.c
>index 516131640cc..75620d579f1 100644
>--- a/src/gallium/drivers/panfrost/pan_screen.c
>+++ b/src/gallium/drivers/panfrost/pan_screen.c
>@@ -697,7 +697,15 @@ panfrost_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_t
> 		RET(((uint64_t []) { 256, 256, 256 }));
> 
> 	case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
>-		RET((uint64_t []) { 256 });
>+                /* On Bifrost and newer, all GPUs can support at least 256 threads
>+                 * regardless of register usage, so we report 256.
>+                 *
>+                 * On Midgard, with maximum register usage, the maximum
>+                 * thread count is only 64. We would like to report 64 here, but
>+                 * the GLES3.1 spec minimum is 128, so we report 128 and limit
>+                 * the register allocation of affected compute kernels.
>+                 */
>+		RET((uint64_t []) { dev->arch >= 6 ? 256 : 128 });
> 
> 	case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
> 		RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
>diff --git a/src/gallium/drivers/r300/ci/r300-rv515-fails.txt b/src/gallium/drivers/r300/ci/r300-rv515-fails.txt
>index d92062c9c3e..201d567c61a 100644
>--- a/src/gallium/drivers/r300/ci/r300-rv515-fails.txt
>+++ b/src/gallium/drivers/r300/ci/r300-rv515-fails.txt
>@@ -25,19 +25,7 @@ dEQP-GLES2.functional.polygon_offset.fixed16_displacement_with_units,Fail
> dEQP-GLES2.functional.polygon_offset.fixed16_render_with_units,Fail
> dEQP-GLES2.functional.polygon_offset.fixed16_factor_1_slope,Fail
> 
>-# Minor errors around the edges
>-dEQP-GLES2.functional.rasterization.interpolation.basic.lines_wide,Fail
>-dEQP-GLES2.functional.rasterization.interpolation.basic.line_strip_wide,Fail
>-dEQP-GLES2.functional.rasterization.interpolation.basic.line_loop_wide,Fail
>-dEQP-GLES2.functional.rasterization.interpolation.projected.lines_wide,Fail
>-dEQP-GLES2.functional.rasterization.interpolation.projected.line_strip_wide,Fail
>-dEQP-GLES2.functional.rasterization.interpolation.projected.line_loop_wide,Fail
>-
> # "Invalid line width at (119, 179) - (119, 180). Detected width of 2, expected 1"
>-dEQP-GLES2.functional.rasterization.primitives.lines,Fail
>-dEQP-GLES2.functional.rasterization.primitives.line_strip,Fail
>-dEQP-GLES2.functional.rasterization.primitives.line_loop,Fail
>-dEQP-GLES2.functional.rasterization.primitives.lines_wide,Fail
> dEQP-GLES2.functional.rasterization.primitives.line_strip_wide,Fail,Fail
> dEQP-GLES2.functional.rasterization.primitives.line_loop_wide,Fail
> 
>diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c
>index 2e9126db5bb..930da10cf2d 100644
>--- a/src/gallium/drivers/r300/r300_state.c
>+++ b/src/gallium/drivers/r300/r300_state.c
>@@ -1218,7 +1218,7 @@ static void* r300_create_rs_state(struct pipe_context* pipe,
> 
>     /* Line control. */
>     line_control = pack_float_16_6x(state->line_width) |
>-        R300_GA_LINE_CNTL_END_TYPE_COMP;
>+        (state->line_smooth ? R300_GA_LINE_CNTL_END_TYPE_COMP : R300_GA_LINE_CNTL_END_TYPE_SQR);
> 
>     /* Enable polygon mode */
>     polygon_mode = 0;
>diff --git a/src/gallium/drivers/r600/sfn/sfn_instr_alugroup.cpp b/src/gallium/drivers/r600/sfn/sfn_instr_alugroup.cpp
>index 379919422bc..93a74ea0ea4 100644
>--- a/src/gallium/drivers/r600/sfn/sfn_instr_alugroup.cpp
>+++ b/src/gallium/drivers/r600/sfn/sfn_instr_alugroup.cpp
>@@ -35,6 +35,25 @@ AluGroup::AluGroup()
>    std::fill(m_slots.begin(), m_slots.end(), nullptr);
> }
> 
>+static bool is_kill(EAluOp op)
>+{
>+   switch (op) {
>+   case op2_kille:
>+   case op2_kille_int:
>+   case op2_killne:
>+   case op2_killne_int:
>+   case op2_killge:
>+   case op2_killge_int:
>+   case op2_killge_uint:
>+   case op2_killgt:
>+   case op2_killgt_int:
>+   case op2_killgt_uint:
>+      return true;
>+   default:
>+      return false;
>+   }
>+}
>+
> bool AluGroup::add_instruction(AluInstr *instr)
> {
>    /* we can only schedule one op that accesses LDS or
>@@ -45,12 +64,17 @@ bool AluGroup::add_instruction(AluInstr *instr)
>    if (instr->has_alu_flag(alu_is_trans)) {
>       auto opinfo = alu_ops.find(instr->opcode());
>       assert(opinfo->second.can_channel(AluOp::t, s_chip_class));
>-      if (add_trans_instructions(instr))
>+      if (add_trans_instructions(instr)) {
>+         if (is_kill(instr->opcode()))
>+            m_has_kill_op = true;
>          return true;
>+      }
>    }
> 
>    if (add_vec_instructions(instr) && !instr->has_alu_flag(alu_is_trans)) {
>       instr->set_parent_group(this);
>+      if (!instr->has_alu_flag(alu_is_lds) && is_kill(instr->opcode()))
>+         m_has_kill_op = true;
>       return true;
>    }
> 
>@@ -61,6 +85,8 @@ bool AluGroup::add_instruction(AluInstr *instr)
>        opinfo->second.can_channel(AluOp::t, s_chip_class) &&
>        add_trans_instructions(instr)) {
>       instr->set_parent_group(this);
>+      if (is_kill(instr->opcode()))
>+         m_has_kill_op = true;
>       return true;
>    }
> 
>diff --git a/src/gallium/drivers/r600/sfn/sfn_instr_alugroup.h b/src/gallium/drivers/r600/sfn/sfn_instr_alugroup.h
>index df58df8204a..2ff31628c2c 100644
>--- a/src/gallium/drivers/r600/sfn/sfn_instr_alugroup.h
>+++ b/src/gallium/drivers/r600/sfn/sfn_instr_alugroup.h
>@@ -87,6 +87,7 @@ public:
>    static bool has_t() { return s_max_slots == 5;}
> 
>    bool addr_for_src() const { return m_addr_for_src;}
>+   bool has_kill_op() const {return m_has_kill_op;}
> 
> private:
>    void forward_set_blockid(int id, int index) override;
>@@ -111,6 +112,7 @@ private:
>    bool m_has_lds_op{false};
>    bool m_addr_is_index{false};
>    bool m_addr_for_src{false};
>+   bool m_has_kill_op{false};
> };
> 
> 
>diff --git a/src/gallium/drivers/r600/sfn/sfn_peephole.cpp b/src/gallium/drivers/r600/sfn/sfn_peephole.cpp
>index 065031287dc..8369b9c6508 100644
>--- a/src/gallium/drivers/r600/sfn/sfn_peephole.cpp
>+++ b/src/gallium/drivers/r600/sfn/sfn_peephole.cpp
>@@ -212,11 +212,22 @@ void ReplaceIfPredicate::visit(AluInstr *alu)
>    if (new_op == op0_nop)
>       return;
> 
>-   /* Have to figure out how to pass the dependency correctly */
>-   /*for (auto& s : alu->sources()) {
>-      if (s->as_register() && s->as_register()->addr())
>+   for (auto& s : alu->sources()) {
>+      auto reg = s->as_register();
>+      /* Protext against propagating
>+       *
>+       *   V = COND(R, X)
>+       *   R = SOME_OP
>+       *   IF (V)
>+       *
>+       * to
>+       *
>+       *   R = SOME_OP
>+       *   IF (COND(R, X))
>+       */
>+      if (reg && !reg->is_ssa())
>          return;
>-   }*/
>+   }
> 
>    m_pred->set_op(new_op);
>    m_pred->set_sources(alu->sources());
>diff --git a/src/gallium/drivers/r600/sfn/sfn_scheduler.cpp b/src/gallium/drivers/r600/sfn/sfn_scheduler.cpp
>index abeac5615da..b4fab307923 100644
>--- a/src/gallium/drivers/r600/sfn/sfn_scheduler.cpp
>+++ b/src/gallium/drivers/r600/sfn/sfn_scheduler.cpp
>@@ -294,7 +294,6 @@ void BlockSheduler::schedule_block(Block& in_block, Shader::ShaderBlocks& out_bl
>    bool have_instr = collect_ready(cir);
> 
>    m_current_block = new Block(in_block.nesting_depth(), in_block.id());
>-
>    assert(m_current_block->id() >= 0);
> 
>    while (have_instr) {
>@@ -569,6 +568,13 @@ bool BlockSheduler::schedule_alu(Shader::ShaderBlocks& out_blocks)
>    if (group->has_lds_group_end())
>       m_current_block->lds_group_end();
> 
>+   if (group->has_kill_op()) {
>+      assert(!group->has_lds_group_start());
>+      start_new_block(out_blocks, Block::alu);
>+      m_current_block->set_instr_flag(Instr::force_cf);
>+   }
>+
>+
>    return success;
> }
> 
>diff --git a/src/gallium/drivers/r600/sfn/sfn_shader_fs.cpp b/src/gallium/drivers/r600/sfn/sfn_shader_fs.cpp
>index 09f2e6d876b..0251e1c8ede 100644
>--- a/src/gallium/drivers/r600/sfn/sfn_shader_fs.cpp
>+++ b/src/gallium/drivers/r600/sfn/sfn_shader_fs.cpp
>@@ -178,6 +178,7 @@ bool FragmentShader::process_stage_intrinsic(nir_intrinsic_instr *intr)
>                                     value_factory().zero(),
>                                     value_factory().zero(),
>                                     {AluInstr::last}));
>+      start_new_block(0);
>       return true;
>    case nir_intrinsic_load_sample_mask_in:
>       if (m_apply_sample_mask) {
>diff --git a/src/gallium/drivers/virgl/virgl_screen.c b/src/gallium/drivers/virgl/virgl_screen.c
>index 3c113f83df4..c3b81e92d63 100644
>--- a/src/gallium/drivers/virgl/virgl_screen.c
>+++ b/src/gallium/drivers/virgl/virgl_screen.c
>@@ -353,6 +353,10 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
>        return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_IMPLICIT_MSAA;
>    case PIPE_CAP_IMAGE_STORE_FORMATTED:
>       return 1;
>+   case PIPE_CAP_MAX_CONSTANT_BUFFER_SIZE_UINT:
>+      if (vscreen->caps.caps.v2.host_feature_check_version >= 13)
>+         return vscreen->caps.caps.v2.max_uniform_block_size;
>+      FALLTHROUGH;
>    default:
>       return u_pipe_screen_get_param_defaults(screen, param);
>    }
>diff --git a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c
>index d3a777aa85c..b545f4216c1 100644
>--- a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c
>+++ b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c
>@@ -445,8 +445,11 @@ get_glsl_type(struct ntv_context *ctx, const struct glsl_type *type)
>          types[i] = get_glsl_type(ctx, glsl_get_struct_field(type, i));
>       ret = spirv_builder_type_struct(&ctx->builder, types,
>                                       glsl_get_length(type));
>-      for (unsigned i = 0; i < glsl_get_length(type); i++)
>-         spirv_builder_emit_member_offset(&ctx->builder, ret, i, glsl_get_struct_field_offset(type, i));
>+      for (unsigned i = 0; i < glsl_get_length(type); i++) {
>+         int32_t offset = glsl_get_struct_field_offset(type, i);
>+         if (offset >= 0)
>+            spirv_builder_emit_member_offset(&ctx->builder, ret, i, offset);
>+      }
>    } else
>       unreachable("Unhandled GLSL type");
> 
>@@ -1808,29 +1811,29 @@ alu_instr_src_components(const nir_alu_instr *instr, unsigned src)
> }
> 
> static SpvId
>-get_alu_src(struct ntv_context *ctx, nir_alu_instr *alu, unsigned src)
>+get_alu_src(struct ntv_context *ctx, nir_alu_instr *alu, unsigned src, SpvId *raw_value)
> {
>-   SpvId raw_value = get_alu_src_raw(ctx, alu, src);
>+   *raw_value = get_alu_src_raw(ctx, alu, src);
> 
>    unsigned num_components = alu_instr_src_components(alu, src);
>    unsigned bit_size = nir_src_bit_size(alu->src[src].src);
>    nir_alu_type type = nir_op_infos[alu->op].input_types[src];
> 
>    if (bit_size == 1)
>-      return raw_value;
>+      return *raw_value;
>    else {
>       switch (nir_alu_type_get_base_type(type)) {
>       case nir_type_bool:
>          unreachable("bool should have bit-size 1");
> 
>       case nir_type_int:
>-         return bitcast_to_ivec(ctx, raw_value, bit_size, num_components);
>+         return bitcast_to_ivec(ctx, *raw_value, bit_size, num_components);
> 
>       case nir_type_uint:
>-         return raw_value;
>+         return *raw_value;
> 
>       case nir_type_float:
>-         return bitcast_to_fvec(ctx, raw_value, bit_size, num_components);
>+         return bitcast_to_fvec(ctx, *raw_value, bit_size, num_components);
> 
>       default:
>          unreachable("unknown nir_alu_type");
>@@ -1905,8 +1908,9 @@ static void
> emit_alu(struct ntv_context *ctx, nir_alu_instr *alu)
> {
>    SpvId src[NIR_MAX_VEC_COMPONENTS];
>+   SpvId raw_src[NIR_MAX_VEC_COMPONENTS];
>    for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++)
>-      src[i] = get_alu_src(ctx, alu, i);
>+      src[i] = get_alu_src(ctx, alu, i, &raw_src[i]);
> 
>    SpvId dest_type = get_dest_type(ctx, &alu->dest.dest,
>                                    nir_op_infos[alu->op].output_type);
>@@ -2083,8 +2087,6 @@ emit_alu(struct ntv_context *ctx, nir_alu_instr *alu)
>    BINOP(nir_op_uge, SpvOpUGreaterThanEqual)
>    BINOP(nir_op_flt, SpvOpFOrdLessThan)
>    BINOP(nir_op_fge, SpvOpFOrdGreaterThanEqual)
>-   BINOP(nir_op_feq, SpvOpFOrdEqual)
>-   BINOP(nir_op_fneu, SpvOpFUnordNotEqual)
>    BINOP(nir_op_frem, SpvOpFRem)
> #undef BINOP
> 
>@@ -2149,6 +2151,23 @@ emit_alu(struct ntv_context *ctx, nir_alu_instr *alu)
>    case nir_op_sge:
>       unreachable("should already be lowered away");
> 
>+   case nir_op_fneu:
>+      assert(nir_op_infos[alu->op].num_inputs == 2);
>+      if (raw_src[0] == raw_src[1])
>+         result =  emit_unop(ctx, SpvOpIsNan, dest_type, src[0]);
>+      else
>+         result = emit_binop(ctx, SpvOpFUnordNotEqual, dest_type, src[0], src[1]);
>+      break;
>+
>+   case nir_op_feq:
>+      assert(nir_op_infos[alu->op].num_inputs == 2);
>+      if (raw_src[0] == raw_src[1])
>+         result =  emit_unop(ctx, SpvOpLogicalNot, dest_type,
>+                             emit_unop(ctx, SpvOpIsNan, dest_type, src[0]));
>+      else
>+         result = emit_binop(ctx, SpvOpFOrdEqual, dest_type, src[0], src[1]);
>+      break;
>+
>    case nir_op_flrp:
>       assert(nir_op_infos[alu->op].num_inputs == 3);
>       result = emit_builtin_triop(ctx, GLSLstd450FMix, dest_type,
>diff --git a/src/gallium/drivers/zink/zink_context.c b/src/gallium/drivers/zink/zink_context.c
>index 59563c6f86f..3c7a9bd998f 100644
>--- a/src/gallium/drivers/zink/zink_context.c
>+++ b/src/gallium/drivers/zink/zink_context.c
>@@ -3400,9 +3400,18 @@ zink_flush(struct pipe_context *pctx,
>    unsigned submit_count = 0;
> 
>    /* triggering clears will force has_work */
>-   if (!deferred && ctx->clears_enabled)
>+   if (!deferred && ctx->clears_enabled) {
>+      /* if fbfetch outputs are active, disable them when flushing clears */
>+      unsigned fbfetch_outputs = ctx->fbfetch_outputs;
>+      if (fbfetch_outputs) {
>+         ctx->fbfetch_outputs = 0;
>+         ctx->rp_changed = true;
>+      }
>       /* start rp to do all the clears */
>       zink_batch_rp(ctx);
>+      ctx->fbfetch_outputs = fbfetch_outputs;
>+      ctx->rp_changed |= fbfetch_outputs > 0;
>+   }
> 
>    if (ctx->needs_present && (flags & PIPE_FLUSH_END_OF_FRAME)) {
>       if (ctx->needs_present->obj->image)
>diff --git a/src/gallium/drivers/zink/zink_device_info.py b/src/gallium/drivers/zink/zink_device_info.py
>index d26908e35ee..d36c915c6ec 100644
>--- a/src/gallium/drivers/zink/zink_device_info.py
>+++ b/src/gallium/drivers/zink/zink_device_info.py
>@@ -160,7 +160,8 @@ EXTENSIONS = [
>        conditions=["$feats.shaderSubgroupClock"]),
>     Extension("VK_EXT_sampler_filter_minmax",
>         alias="reduction",
>-	properties=True),
>+        properties=True,
>+        conditions=["$props.filterMinmaxSingleComponentFormats"]),
>     Extension("VK_EXT_custom_border_color",
>         alias="border_color",
>         properties=True,
>diff --git a/src/gallium/drivers/zink/zink_render_pass.c b/src/gallium/drivers/zink/zink_render_pass.c
>index 1467d001212..ee511c490c9 100644
>--- a/src/gallium/drivers/zink/zink_render_pass.c
>+++ b/src/gallium/drivers/zink/zink_render_pass.c
>@@ -631,6 +631,8 @@ begin_render_pass(struct zink_context *ctx)
>    infos.pAttachments = att;
>    if (!prep_fb_attachments(ctx, att))
>       return 0;
>+   /* this can be set if fbfetch is activated */
>+   ctx->rp_changed = false;
> #ifndef NDEBUG
>    const unsigned cresolve_offset = ctx->fb_state.nr_cbufs + !!ctx->fb_state.zsbuf;
>    for (int i = 0; i < ctx->fb_state.nr_cbufs; i++) {
>diff --git a/src/gallium/drivers/zink/zink_screen.c b/src/gallium/drivers/zink/zink_screen.c
>index 54d44714849..cec8a7add2a 100644
>--- a/src/gallium/drivers/zink/zink_screen.c
>+++ b/src/gallium/drivers/zink/zink_screen.c
>@@ -683,7 +683,7 @@ zink_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
>       return screen->info.props.limits.maxTexelGatherOffset;
> 
>    case PIPE_CAP_SAMPLER_REDUCTION_MINMAX_ARB:
>-      return screen->vk_version >= VK_MAKE_VERSION(1,2,0) || screen->info.have_EXT_sampler_filter_minmax;
>+      return screen->info.feats12.samplerFilterMinmax || screen->info.have_EXT_sampler_filter_minmax;
> 
>    case PIPE_CAP_FS_FINE_DERIVATIVE:
>       return 1;
>diff --git a/src/gallium/drivers/zink/zink_state.c b/src/gallium/drivers/zink/zink_state.c
>index 287655459c4..0b7978d20dd 100644
>--- a/src/gallium/drivers/zink/zink_state.c
>+++ b/src/gallium/drivers/zink/zink_state.c
>@@ -604,7 +604,7 @@ zink_create_rasterizer_state(struct pipe_context *pctx,
>    }
> 
>    if (!rs_state->line_stipple_enable) {
>-      state->base.line_stipple_factor = 0;
>+      state->base.line_stipple_factor = 1;
>       state->base.line_stipple_pattern = UINT16_MAX;
>    }
> 
>diff --git a/src/gallium/frontends/va/image.c b/src/gallium/frontends/va/image.c
>index 19d0f69121a..0255cf59ced 100644
>--- a/src/gallium/frontends/va/image.c
>+++ b/src/gallium/frontends/va/image.c
>@@ -256,9 +256,12 @@ vlVaDeriveImage(VADriverContextP ctx, VASurfaceID surface, VAImage *image)
>                                    PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE))
>          return VA_STATUS_ERROR_OPERATION_FAILED;
>    } else {
>-      for (i = 0; i < ARRAY_SIZE(derive_progressive_disallowlist); i++)
>-         if ((strcmp(derive_progressive_disallowlist[i], proc) == 0))
>-            return VA_STATUS_ERROR_OPERATION_FAILED;
>+         if(!screen->get_video_param(screen, PIPE_VIDEO_PROFILE_UNKNOWN,
>+                                   PIPE_VIDEO_ENTRYPOINT_BITSTREAM,
>+                                   PIPE_VIDEO_SUPPORTS_CONTIGUOUS_PLANES_MAP))
>+            for (i = 0; i < ARRAY_SIZE(derive_progressive_disallowlist); i++)
>+               if ((strcmp(derive_progressive_disallowlist[i], proc) == 0))
>+                  return VA_STATUS_ERROR_OPERATION_FAILED;
>    }
> 
>    surfaces = surf->buffer->get_surfaces(surf->buffer);
>diff --git a/src/gallium/include/pipe/p_video_enums.h b/src/gallium/include/pipe/p_video_enums.h
>index 7d157364479..c195a70b0c2 100644
>--- a/src/gallium/include/pipe/p_video_enums.h
>+++ b/src/gallium/include/pipe/p_video_enums.h
>@@ -105,6 +105,10 @@ enum pipe_video_cap
>    PIPE_VIDEO_CAP_VPP_MAX_OUTPUT_HEIGHT = 23,
>    PIPE_VIDEO_CAP_VPP_MIN_OUTPUT_WIDTH = 24,
>    PIPE_VIDEO_CAP_VPP_MIN_OUTPUT_HEIGHT = 25,
>+   /* If true, when mapping planar textures like NV12 or P016 the mapped buffer contains
>+   all the planes contiguously. This allows for use with some frontends functions that
>+   require this like vaDeriveImage */
>+   PIPE_VIDEO_SUPPORTS_CONTIGUOUS_PLANES_MAP = 27,
> };
> 
> /* To be used with PIPE_VIDEO_CAP_VPP_ORIENTATION_MODES and for VPP state*/
>diff --git a/src/gallium/targets/opencl/meson.build b/src/gallium/targets/opencl/meson.build
>index 14df6b86f7f..8f9d7ac5a53 100644
>--- a/src/gallium/targets/opencl/meson.build
>+++ b/src/gallium/targets/opencl/meson.build
>@@ -58,7 +58,7 @@ if can_check_clang
> else
>   dep_clang_usable = true
> endif
>-if not (dep_clang.found() and dep_clang_usable)
>+if not _shared_llvm or not (dep_clang.found() and dep_clang_usable)
>   dep_clang = [
>     cpp.find_library('clangCodeGen', dirs : llvm_libdir),
>     cpp.find_library('clangFrontendTool', dirs : llvm_libdir),
>diff --git a/src/intel/ds/intel_tracepoints.py b/src/intel/ds/intel_tracepoints.py
>index 6efcb7ba48c..9085cc3de89 100644
>--- a/src/intel/ds/intel_tracepoints.py
>+++ b/src/intel/ds/intel_tracepoints.py
>@@ -61,8 +61,7 @@ def define_tracepoints(args):
>                  tp_args=[Arg(type='uint16_t', var='width', c_format='%hu'),
>                           Arg(type='uint16_t', var='height', c_format='%hu'),
>                           Arg(type='uint8_t', var='att_count', c_format='%hhu'),
>-                          Arg(type='uint8_t', var='msaa', c_format='%hhu'),
>-                          Arg(type='uint32_t', var='subpass_count', c_format='%u'),])
>+                          Arg(type='uint8_t', var='msaa', c_format='%hhu'),])
> 
>     begin_end_tp('dyn_render_pass',
>                  tp_args=[Arg(type='uint16_t', var='width', c_format='%hu'),
>diff --git a/src/intel/vulkan/anv_descriptor_set.c b/src/intel/vulkan/anv_descriptor_set.c
>index b2ecf0d447f..1aa76424caa 100644
>--- a/src/intel/vulkan/anv_descriptor_set.c
>+++ b/src/intel/vulkan/anv_descriptor_set.c
>@@ -784,8 +784,8 @@ VkResult anv_CreatePipelineLayout(
> 
>    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO);
> 
>-   layout = vk_object_alloc(&device->vk, pAllocator, sizeof(*layout),
>-                            VK_OBJECT_TYPE_PIPELINE_LAYOUT);
>+   layout = vk_object_zalloc(&device->vk, pAllocator, sizeof(*layout),
>+                             VK_OBJECT_TYPE_PIPELINE_LAYOUT);
>    if (layout == NULL)
>       return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
> 
>diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
>index 240630d8412..e2cc788a283 100644
>--- a/src/intel/vulkan/genX_cmd_buffer.c
>+++ b/src/intel/vulkan/genX_cmd_buffer.c
>@@ -7182,6 +7182,12 @@ void genX(CmdEndRendering)(
>    }
> #endif
> 
>+   trace_intel_end_render_pass(&cmd_buffer->trace,
>+                               gfx->render_area.extent.width,
>+                               gfx->render_area.extent.height,
>+                               gfx->color_att_count,
>+                               gfx->samples);
>+
>    anv_cmd_buffer_reset_rendering(cmd_buffer);
> }
> 
>diff --git a/src/mesa/main/glthread_marshal.h b/src/mesa/main/glthread_marshal.h
>index 5268ae2a472..0c0f74b6bf6 100644
>--- a/src/mesa/main/glthread_marshal.h
>+++ b/src/mesa/main/glthread_marshal.h
>@@ -509,6 +509,9 @@ _mesa_glthread_PushAttrib(struct gl_context *ctx, GLbitfield mask)
>    if (ctx->GLThread.ListMode == GL_COMPILE)
>       return;
> 
>+   if (ctx->GLThread.AttribStackDepth >= MAX_ATTRIB_STACK_DEPTH)
>+      return;
>+
>    struct glthread_attrib_node *attr =
>       &ctx->GLThread.AttribStack[ctx->GLThread.AttribStackDepth++];
> 
>@@ -533,6 +536,9 @@ _mesa_glthread_PopAttrib(struct gl_context *ctx)
>    if (ctx->GLThread.ListMode == GL_COMPILE)
>       return;
> 
>+   if (ctx->GLThread.AttribStackDepth == 0)
>+      return;
>+
>    struct glthread_attrib_node *attr =
>       &ctx->GLThread.AttribStack[--ctx->GLThread.AttribStackDepth];
>    unsigned mask = attr->Mask;
>@@ -552,12 +558,36 @@ _mesa_glthread_PopAttrib(struct gl_context *ctx)
>    }
> }
> 
>+static bool
>+is_matrix_stack_full(struct gl_context *ctx, gl_matrix_index idx)
>+{
>+   int max_stack_depth = 0;
>+   if (M_MODELVIEW == ctx->GLThread.MatrixIndex) {
>+      max_stack_depth = MAX_MODELVIEW_STACK_DEPTH;
>+   } else if (M_PROJECTION == ctx->GLThread.MatrixIndex) {
>+      max_stack_depth = MAX_PROJECTION_STACK_DEPTH;
>+   } else if (M_PROGRAM_LAST >= ctx->GLThread.MatrixIndex) {
>+      max_stack_depth = MAX_PROGRAM_MATRIX_STACK_DEPTH;
>+   } else if (M_TEXTURE_LAST >= ctx->GLThread.MatrixIndex) {
>+      max_stack_depth = MAX_TEXTURE_STACK_DEPTH;
>+   }
>+   assert(max_stack_depth);
>+
>+   if (ctx->GLThread.MatrixStackDepth[idx] + 1 >= max_stack_depth)
>+      return true;
>+
>+   return false;
>+}
>+
> static inline void
> _mesa_glthread_MatrixPushEXT(struct gl_context *ctx, GLenum matrixMode)
> {
>    if (ctx->GLThread.ListMode == GL_COMPILE)
>       return;
> 
>+   if (is_matrix_stack_full(ctx, _mesa_get_matrix_index(ctx, matrixMode)))
>+      return;
>+
>    ctx->GLThread.MatrixStackDepth[_mesa_get_matrix_index(ctx, matrixMode)]++;
> }
> 
>@@ -567,6 +597,9 @@ _mesa_glthread_MatrixPopEXT(struct gl_context *ctx, GLenum matrixMode)
>    if (ctx->GLThread.ListMode == GL_COMPILE)
>       return;
> 
>+   if (ctx->GLThread.MatrixStackDepth[_mesa_get_matrix_index(ctx, matrixMode)] == 0)
>+      return;
>+
>    ctx->GLThread.MatrixStackDepth[_mesa_get_matrix_index(ctx, matrixMode)]--;
> }
> 
>@@ -587,6 +620,9 @@ _mesa_glthread_PushMatrix(struct gl_context *ctx)
>    if (ctx->GLThread.ListMode == GL_COMPILE)
>       return;
> 
>+   if (is_matrix_stack_full(ctx, ctx->GLThread.MatrixIndex))
>+      return;
>+
>    ctx->GLThread.MatrixStackDepth[ctx->GLThread.MatrixIndex]++;
> }
> 
>@@ -596,6 +632,9 @@ _mesa_glthread_PopMatrix(struct gl_context *ctx)
>    if (ctx->GLThread.ListMode == GL_COMPILE)
>       return;
> 
>+   if (ctx->GLThread.MatrixStackDepth[ctx->GLThread.MatrixIndex] == 0)
>+      return;
>+
>    ctx->GLThread.MatrixStackDepth[ctx->GLThread.MatrixIndex]--;
> }
> 
>diff --git a/src/mesa/vbo/vbo_exec_api.c b/src/mesa/vbo/vbo_exec_api.c
>index cff420ee68e..f7faef52f5c 100644
>--- a/src/mesa/vbo/vbo_exec_api.c
>+++ b/src/mesa/vbo/vbo_exec_api.c
>@@ -855,7 +855,8 @@ _mesa_Begin(GLenum mode)
>     * leave dlist.c's dispatch table in place.
>     */
>    if (ctx->GLThread.enabled) {
>-      ctx->CurrentServerDispatch = ctx->Exec;
>+      if (ctx->CurrentServerDispatch == ctx->OutsideBeginEnd)
>+         ctx->CurrentServerDispatch = ctx->Exec;
>    } else if (ctx->CurrentClientDispatch == ctx->OutsideBeginEnd) {
>       ctx->CurrentClientDispatch = ctx->CurrentServerDispatch = ctx->Exec;
>       _glapi_set_dispatch(ctx->CurrentClientDispatch);
>@@ -914,7 +915,10 @@ _mesa_End(void)
>    ctx->Exec = ctx->OutsideBeginEnd;
> 
>    if (ctx->GLThread.enabled) {
>-      ctx->CurrentServerDispatch = ctx->Exec;
>+      if (ctx->CurrentServerDispatch == ctx->BeginEnd ||
>+          ctx->CurrentServerDispatch == ctx->HWSelectModeBeginEnd) {
>+         ctx->CurrentServerDispatch = ctx->Exec;
>+      }
>    } else if (ctx->CurrentClientDispatch == ctx->BeginEnd ||
>               ctx->CurrentClientDispatch == ctx->HWSelectModeBeginEnd) {
>       ctx->CurrentClientDispatch = ctx->CurrentServerDispatch = ctx->Exec;
>diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c
>index d493f4219e3..aee4f283bb8 100644
>--- a/src/panfrost/midgard/midgard_ra.c
>+++ b/src/panfrost/midgard/midgard_ra.c
>@@ -518,6 +518,18 @@ allocate_registers(compiler_context *ctx, bool *spilled)
>                         }
>                 }
> 
>+                /* Anything read as 16-bit needs proper alignment to ensure the
>+                 * resulting code can be packed.
>+                 */
>+                mir_foreach_src(ins, s) {
>+                        unsigned src_size = nir_alu_type_get_type_size(ins->src_types[s]);
>+                        if (src_size == 16 && ins->src[s] < SSA_FIXED_MINIMUM)
>+                                min_bound[ins->src[s]] = MAX2(min_bound[ins->src[s]], 8);
>+                }
>+
>+                /* Everything after this concerns only the destination, not the
>+                 * sources.
>+                 */
>                 if (ins->dest >= SSA_FIXED_MINIMUM) continue;
> 
>                 unsigned size = nir_alu_type_get_type_size(ins->dest_type);
>@@ -547,12 +559,6 @@ allocate_registers(compiler_context *ctx, bool *spilled)
>                 if (size == 16 && min_alignment[dest] != 4)
>                         min_bound[dest] = 8;
> 
>-                mir_foreach_src(ins, s) {
>-                        unsigned src_size = nir_alu_type_get_type_size(ins->src_types[s]);
>-                        if (src_size == 16 && ins->src[s] < SSA_FIXED_MINIMUM)
>-                                min_bound[ins->src[s]] = MAX2(min_bound[ins->src[s]], 8);
>-                }
>-
>                 /* We don't have a swizzle for the conditional and we don't
>                  * want to muck with the conditional itself, so just force
>                  * alignment for now */
>diff --git a/src/util/00-mesa-defaults.conf b/src/util/00-mesa-defaults.conf
>index 8fd2b366f3e..c161ebd7c42 100644
>--- a/src/util/00-mesa-defaults.conf
>+++ b/src/util/00-mesa-defaults.conf
>@@ -153,6 +153,10 @@ TODO: document the other workarounds.
>             <option name="allow_glsl_builtin_variable_redeclaration" value="true" />
>         </application>
> 
>+        <application name="Exanima" executable="Exanima.exe">
>+            <option name="glsl_zero_init" value="true"/>
>+        </application>
>+
>         <application name="Full Bore" executable="fullbore">
>             <option name="allow_glsl_builtin_variable_redeclaration" value="true" />
>         </application>
>@@ -831,6 +835,9 @@ TODO: document the other workarounds.
>             <option name="radeonsi_zerovram" value="true" />
>             <option name="radeonsi_clamp_div_by_zero" value="true" />
>         </application>
>+        <application name="Exanima" executable="Exanima.exe">
>+            <option name="radeonsi_zerovram" value="true"/>
>+        </application>
>         <application name="Rocket League" executable="RocketLeague">
>             <option name="radeonsi_zerovram" value="true" />
>         </application>
>diff --git a/src/virtio/virtio-gpu/virgl_hw.h b/src/virtio/virtio-gpu/virgl_hw.h
>index eafc0b41912..653a4183fd4 100644
>--- a/src/virtio/virtio-gpu/virgl_hw.h
>+++ b/src/virtio/virtio-gpu/virgl_hw.h
>@@ -603,6 +603,7 @@ struct virgl_caps_v2 {
>         uint32_t max_shader_sampler_views;
>         struct virgl_supported_format_mask supported_multisample_formats;
>         uint32_t max_const_buffer_size[6]; // PIPE_SHADER_TYPES
>+        uint32_t max_uniform_block_size;
> };
> 
> union virgl_caps {
>diff --git a/src/vulkan/runtime/vk_pipeline_cache.c b/src/vulkan/runtime/vk_pipeline_cache.c
>index 6fa9b3ff632..f837ed3d482 100644
>--- a/src/vulkan/runtime/vk_pipeline_cache.c
>+++ b/src/vulkan/runtime/vk_pipeline_cache.c
>@@ -337,7 +337,7 @@ vk_pipeline_cache_lookup_object(struct vk_pipeline_cache *cache,
>    if (object == NULL) {
> #ifdef ENABLE_SHADER_CACHE
>       struct disk_cache *disk_cache = cache->base.device->physical->disk_cache;
>-      if (disk_cache != NULL) {
>+      if (disk_cache != NULL && cache->object_cache != NULL) {
>          cache_key cache_key;
>          disk_cache_compute_key(disk_cache, key_data, key_size, cache_key);
> 
>diff --git a/src/vulkan/wsi/meson.build b/src/vulkan/wsi/meson.build
>index fd48474b98f..deaaeae3025 100644
>--- a/src/vulkan/wsi/meson.build
>+++ b/src/vulkan/wsi/meson.build
>@@ -84,6 +84,8 @@ else
>     # Instruct users of this library to link with --whole-archive.  Otherwise,
>     # our weak function overloads may not resolve properly.
>     link_whole : libvulkan_wsi,
>-    dependencies : idep_vulkan_wsi_headers
>+    dependencies : [
>+      idep_vulkan_wsi_headers, dep_libudev
>+    ]
>   )
> endif

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Attachments on bug 44472: 12006 | 12007 | 12008